Semiconductor Devices Modeling for IC Technology Application

Henok Abebe
Sandia National Laboratories

Gordon Moore predicted in 1965 that the number of transistors per integrated circuit chip would continue to double in each technology generation (Moore's Law). For decades, chip makers have succeeded in shrinking chip geometries using individual transistors scaling and able to improve transistor performance. Eventually, improving transistor performance using the scaling rules will come to an end, currently predicted to be 2019. Further dimensional scaling of the transistor devices in the nanometer range increases the device leakage power and short channel effects with each technology generation. Transistor modeling for circuit simulation application is also becoming complicated with large number of model parameters. The talk will give an overview of CGU clinic research effort on transistor compact modeling in collaboration with USC/ISI MOSIS (1997-2012).